The semiconductor industry is entering an era in which continued performance scaling can no longer rely solely on transistor shrinkage. Chiplets, advanced packaging, and 3D IC architectures are becoming key development directions, reshaping how IC and packaging teams design, integrate, and verify systems.

In this article, we explore six key trends driving the shift toward 3D ICs and how Siemens is helping design teams adapt to the increasingly complex requirements of next-generation semiconductor systems.

Why is advanced packaging critical to scaling AI performance?

Between 2012 and 2018, AI compute demand doubled approximately every 3.4 months. More recently, this pace has slowed to roughly a doubling every seven months. This growth is pushing transistor density and bandwidth requirements beyond what monolithic SoCs can realistically deliver. At the same time, the industry is approaching fundamental physical limits in feature scaling. Advanced lithography limits reticle size to approximately 858 mm²—the maximum mask pattern area that can be printed on a wafer—while increasing defect rates and lower yields at advanced process nodes mean that economically viable dies often need to be significantly smaller.

The side-by-side integration of disaggregated dies in advanced 2.5D packages is also approaching the limits of die-to-die interconnect technology, while simultaneously reaching form-factor constraints in end systems.

As a result, scaling next-generation AI and HPC systems requires a fundamental architectural shift, where performance gains come from greater proximity in three-dimensional space. Logic and memory must be disaggregated and then reintegrated across wafers, vertically stacked structures, and advanced packages while maintaining thermal, electrical, and mechanical reliability.

Trend 1: Technology scaling and expanded integration

The advanced packaging roadmap is moving toward smaller feature sizes to achieve higher integration density and better performance at lower power. As thermocompression bonding approaches its integration limits, hybrid bonding is expected to push 3D interconnect pitches toward 1 µm and below. In addition, AI and HPC computing providers are exploring wafer-level and panel-level architectures to bring increasing amounts of compute closer together.

A notable industry example is Cerebras with its WSE-3 accelerator, which integrates approximately four trillion transistors across an active area of about 215 × 215 mm. Meanwhile, foundries are pursuing more modular wafer-scale strategies. TSMC’s SoW-X assembles pre-tested logic, memory, and I/O dies onto a reconstructed wafer using wafer-level redistribution layers (RDL) and local silicon interconnects (LSI), with a publicly stated target of up to 16 full-reticle ASICs and approximately 80 HBM4 stacks.

As a result, EDA requirements are shifting toward wafer-scale multiphysics system simulation to accurately model power, thermal, signal, and mechanical interactions in highly integrated architectures.

Trend 2: Unlocking 3D CPO for AI systems

Optical interconnects, with their low transmission loss over long distances, are essential components of data-center-scale compute engines and even larger systems. As AI systems continue to scale, power consumption from high-speed electrical links increases while bandwidth density approaches physical limits.

Co-Packaged Optics (CPO) has emerged as a key enabler for next-generation AI performance by tightly integrating electronic ICs (EICs) and photonic ICs (PICs) within the same package. By bringing optical I/O closer to the xPU or switch silicon, CPO reduces interconnect distances from tens of centimeters to just a few millimeters, improving signal integrity and bandwidth density.

Foundries and OSAT providers have demonstrated that this level of integration is practical. Platforms such as TSMC’s Compact Universal Photonic Engine (COUPE) show how electronic dies can be stacked directly on photonic dies using advanced 3D packaging technologies.

From a design perspective, CPO introduces more demanding device validation and testing requirements. In 3D architectures, hybrid bonding, die thinning, and vertical heat flow create complex thermo-mechanical stresses that can affect alignment accuracy and long-term reliability. Thermo-optic effects must also be carefully analyzed because temperature variations can shift optical wavelengths.

Trend 3: Cooling silicon “skyscrapers” with in-package microfluidics

By vertically stacking memory into multi-layer silicon “skyscrapers,” designers can shorten interconnect lengths and achieve higher bandwidth without routing horizontally across the entire package. The challenge is that DRAM is significantly more temperature-sensitive than logic. While advanced logic dies may operate at temperatures up to 125 °C, DRAM is typically limited to around 85 °C. As memory is brought closer together in stacked systems, thermal headroom quickly becomes a primary design concern. Keeping HBM within specification while maintaining high logic power density requires more aggressive cooling strategies.

Emerging microfluidic approaches address this challenge by bringing coolant to within just a few micrometers of active transistors. Micro-scale trenches or channels are etched to increase contact area, significantly improving heat-transfer efficiency.

As cooling becomes an integral part of package architecture, accurate 3D models of microfluidic channel networks become essential, together with multiphysics solvers capable of handling coupled electrical, thermal, and mechanical effects.

Trend 4: Material innovation enabling AI, HPC, and 6G applications

Recent advances in manufacturing technology and materials science have significantly accelerated innovation in semiconductors and electronic packaging.

First, glass substrates are attracting increasing attention for large-area and high-frequency designs. Mechanically, glass has a coefficient of thermal expansion (~3.2 ppm/°C) close to that of silicon, helping reduce package warpage by nearly 50% for large substrates. Electrically, glass’s low dielectric constant supports reliable signal transmission as data rates approach 224 Gbps and RF frequencies move toward 100 GHz for 6G systems. Manufacturing advances such as Laser-Induced Deep Etching (LIDE) and fine-pitch Through-Glass Vias (TGVs) are making glass increasingly suitable for heterogeneous integration of high-frequency front-end chips, antennas, and low-loss interconnects.

However, glass is brittle. As substrates are thinned to meet electrical and form-factor requirements, interface stress, fracture risk, and stress discontinuities between layers become major design concerns. Accurately modeling these effects early in the design process will be critical.

Second, polymer-based packaging materials—previously regarded primarily as a means of bonding or encapsulating chips—have become important contributors to reliability, performance, and cost. As chips move toward chiplets and 2.5D/3D stacks, mechanical stress becomes a significant challenge. Polymers absorb these stresses; without them, yield can decline and long-term reliability can be compromised.

Trend 5: Growing demand for mmWave antenna-in-package design

As the industry accelerates 6G research and prototyping, adoption of antenna-in-package (AiP) technology is approaching a major inflection point.

Operation in sub-THz and >100 GHz frequency ranges introduces fundamental constraints related to link loss, antenna efficiency, and phase accuracy. As wavelengths become significantly shorter, antenna elements become small enough to integrate directly within the package. This enables high-density phased-array architectures with advanced beamforming, tighter RF-to-antenna coupling, and lower losses by eliminating board-level routing.

Recent AiP architectures increasingly leverage vertical 3D integration. Multiple dielectric layers, embedded ground planes, and parasitic elements are stacked within micrometers of the RF IC. This approach minimizes electrical path lengths, reduces parasitic loss, and avoids losses associated with PCB-level feed routing.

However, integrating antennas into the package significantly tightens manufacturing and design tolerances. At sub-THz frequencies, micrometer-scale variations in dielectric thickness, surface roughness, via geometry, or layer alignment can substantially degrade system efficiency, bandwidth, and beamforming accuracy. The close proximity of RF, digital logic, and power distribution networks also increases the risk of coupling, EMI/EMC issues, and thermally induced RF drift.

Trend 6: 3D AI for 3D IC design

As 3D IC complexity continues to increase, traditional rule-based automation and isolated point optimizers are no longer sufficient to manage the scale, coupling, and expanding design space created by advanced packaging. This is driving a new shift toward AI-native workflows specifically designed for 3D ICs, where large language models (LLMs), optimization engines, and domain-specific AI operate throughout the design, analysis, and verification lifecycle. Leading EDA providers such as Siemens are already applying AI to design space exploration, routing, multiphysics optimization, DFT, and many other areas.

The next step is workflow orchestration powered by generative AI and agentic AI. For example, during early architectural stages, LLMs can transform human-readable inputs—such as PDF specifications, requirements, and design intent—into structured, machine-ready formats, enabling teams to move from intent to executable analysis in hours instead of weeks.

During implementation, AI can help accelerate exploration of massive design spaces across stacks and packages, learning from previous designs to converge more quickly under real-world manufacturing constraints.

At signoff, LLMs can consolidate multidisciplinary results into concise, auditable summaries that communicate the reasoning, safety margins, and remaining risks, closing the loop between analysis and decision-making.

This “3D AI” model is not intended to replace engineers. Instead, it is designed to scale human expertise, enabling teams to explore more alternatives earlier, converge faster, and make decisions with deeper insight.

(Source: Siemens)

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